1. Technical Field
The present invention generally relates to a method for fabricating a semiconductor device, and more specifically, to a method for fabricating a semiconductor device with a FinFET.
2. Description of the Related Art
Because semiconductor devices are highly integrated, two-dimensional transistor structures are limited in many aspects. Specifically, two-dimensional transistor structures cannot meet the current drivability requirements of high-speed semiconductor devices. To solve these limitations, a FinFET has been proposed. Because a FinFET comprises a three-sided channel, a FinFET has a very high current drivability and improved back bias dependency.
FIGS. 1A to 1C illustrate a method for fabricating a conventional FinFET. The top diagrams in each of FIGS. 1A to 1C illustrate plan view layouts of a FinFET and the bottom diagrams in each of FIGS. 1A to 1C illustrate sectional views taken along line I-I′.
Referring to FIG. 1A, a shallow trench isolation (STI) process is performed on a semiconductor substrate 11 to form a field oxide layer 12 defining an active region 13. Referring to FIG. 1B, a fin mask 14 with straight lines and a spacing pattern is then formed on semiconductor substrate 11. Field oxide layer 12 is then recessed (15A) to a predetermined thickness, using fin mask 14 as an etch barrier, to form a fin active region pattern 15B.
Referring to FIG. 1C, fin mask 14 is then removed and a gate insulation layer 16 is formed on fin active region pattern 15B, and subsequently, a gate electrode 17 is formed on gate insulation layer 16. A passing gate is then formed in a region referenced by symbol “P” in FIG. 1C. The passing gate is a gate that is formed in a region where no channel is formed. The passing gate can have an influence on a storage node SN of a DRAM, and as such, degrade device characteristics like data retention time. Therefore, it is preferable to not etch field oxide layer 12 formed in region P during fabrication of a FinFET.
FIG. 2A illustrates a sectional view taken along line II-II′ of FIG. 1C. As illustrated, three sides of fin active region pattern 15B are used as a channel. However, because the three sides of fin active region pattern 15B, acting as a channel, are easily opened, it is difficult to increase the threshold voltage above a predetermined level.
Accordingly, in order to increase the threshold voltage, side doping 18 may be performed on the sidewalls of fin active region pattern 15B using an ion implantation process under conditions of BF2, 60 keV, 2.0×1013 atoms/cm3, and 30° tilt; and top doping 19 may be performed on the top of fin active region pattern 15B under conditions of BF2, 20 keV, 0-2.0×1013 atoms/cm3, and 7° tilt, thereby forming a phosphorous-doped polysilicon gate electrode. Meanwhile, a heavily doped N-type (N+) polysilicon gate electrode is used in a cell region. For example, an in-situ phosphorous-doped polysilicon gate electrode can be used as the N+ polysilicon gate electrode.
FIG. 2B illustrates the measurement results of threshold voltages of cell transistors in 1,000 cell arrays. Specifically, FIG. 2B illustrates cell threshold voltages (1K cell Vtsat) with respect to top dose during top doping. Even though the dose is split during the top doping, it is still difficult to increase the threshold voltage above about 0.5 V. Therefore, conventional FinFETs cannot be used as cell transistors of a DRAM requiring a high threshold voltage of approximately 0.8 V or more. If the threshold voltage cannot be increased above a predetermined level, off leakage characteristics may be greatly degraded in a DRAM.